The BrainScaleS system is based on physical (analogue or mixed-signal) emulations of neuron, synapse and plasticity models with digital connectivity, running up to ten thousand times faster than real time.
The BrainScaleS system (NM-PM-1) contains 20 8-inch silicon wafers in 180 nm process technology. Each wafer incorporates 50 x 106 plastic synapses and 200,000 biologically realistic neurons. The system does not execute pre-programmed code but evolves according to the physical properties of the electronic devices, running at up to 10 thousand times faster than real time.
The SpiNNaker system is based on numerical models running in real time on custom digital multicore chips using the ARM architecture. The SpiNNaker system (NM-MC-1) provides almost 30,000 custom digital chips, each with eighteen cores and a shared local 128 Mbyte RAM, giving a total of over 500,000 cores.
A single chip can simulate 16,000 neurons with eight million plastic synapses running in real time with an energy budget of 1W.
Towards the next generation HBP machines
Whereas the base chips now operating in the two large-scale machines have been developed in various national and European projects over the last decade, next generation chips are now being developed in the HBP. Those next generation chips will be the basis for the next generation of large-scale machines to be operational towards the end of the current project planning around 2023. In the Ramp-Up Phase first prototypes for both complementary approaches, SpiNNaker and BrainScaleS, have been designed and produced. Both chip prototypes make use of the huge technological progress in solid state manufacturing technology and are a result of a close collaboration with neuroscientists in the HBP. Special emphasis is put on greatly improved capabilities for efficient implementation of learning and development.
Layout drawing of the third HICANN-DLS prototype ASIC for the BrainScaleS 2 system.
|Prototype SpiNNaker-2 test chip and small-scale system (Santos)|